1. Field of the Invention
The present invention relates generally to MOS (Metal-Oxide-Semiconductor) field effect transistors (referred to as "SOI-MOSFET" hereinafter) formed in semiconductor layers on insulator substrates, and more particularly, to body regions for improving a withstand voltage between source and drain, and for preventing a kink effect on a curve representing a relation between a drain voltage and a drain current.
2. Description of The Background Art
FIG. 16 is a plan view of a conventional SOI-MOSFET, and FIGS. 17 and 18 are sectional views taken along a line I--I and a line J--J in FIG. 16, respectively. Referring to these drawings, an insulator layer 2 formed on a silicon substrate 1 and a silicon film is formed on the insulator layer 2. A channel region 6 having a low-concentration of p type impurity is formed in the silicon layer 3 surrounded by an isolation oxide film 10, and a source region 8 and a drain region 9 having a high-concentration of n type is formed in contact with one and the other sides of the channel region 6, respectively. In addition, in the silicon layer 3, a body region 27 having a high-concentration of p type impurity is formed in contact with one end of the elongate channel region 6 provided between the source region 8 and the drain region 9.
A gate dielectric thin film 4 is formed on the channel region 6 and a gate electrode 5 is formed on the dielectric thin film 4. The silicon layer 3 and the gate electrode 5 are covered with an interlayer insulating film 11. Contact holes 13a, 13b, 13c and 13d are made in the interlayer insulating film 11, and conductors 15a, 15b, 15c and 15d are connected through the contact holes to the source region 8, the gate electrode 5, the drain region 9 and the body region 27, respectively.
In the SOI-MOSFET structured as the foregoing, when a positive voltage is applied to the gate electrode 5, n type carriers (electrons) are induced in an upper partial layer of the p type channel region 6, thereby inverting the upper partial layer to the same n conductivity type as those of the source region 8 and the drain region 9, allowing a current to flow between the source region 8 and the drain region 9. In addition, since a concentration of the n type carriers induced in the upper partial layer is changed depending on a gate voltage, a current amount flowing through the channel region 6 can be controlled by the gate voltage. This is a principle of an operation of the MOSFET.
When a voltage applied between the source region 8 and the drain region 9 is high, the carriers are accelerated to a high speed in the channel region 6. The carriers accelerated in the channel region 6 generate pairs of electron and hole near the drain region 9 due to impact ionization. Although the generated electrons flow into the n.sup.+ type drain region 9, the holes flow into the body region 27 having a higher concentration of p type impurity than that of the channel region 6 to be drawn out through the conductor 15d. More specifically, the body region 27 serves to remove the excessive holes generated by impact ionization from the channel region 6.
In case no body region 27 is provided, when the silicon layer 3 is thick (for example about 5000A), there occurs unfavorable kink effect on a curve showing a relation between a drain voltage and a drain current. The kink effect is described in "IEEE Electron Device Letter, Vol. 9, No. 2, pp. 97-99, 1988.
On the other hand, a thin film SOI-MOSFET having a silicon layer 3 so thin (for example, a thickness of 500A-1500A) that the whole channel region 6 becomes a depletion layer by an application of the gate voltage has excellent characteristics as compared with an SOI-MOSFET having a thick silicon layer 3. For example, in the thin film SOI-MOSFET, undesirable short channel effect is reduced and a leak current between source and drain is reduced.
However, in case no body region 27 is provided in the thin film SOI-MOSFET, the holes generated by impact ionization are stored in the channel layer 6 which is completely depleted and has a high potential, so that the potential is further increased. Accordingly, an electrical barrier between the source region 8 and the channel region 6 is lowered, inducing a sudden injection of the electrons from the source region 8 into the channel region 6. As a result, the channel current is rapidly increased. More specifically, in general the thin film SOI-MOSFET generally has a considerably low withstand voltage between source and drain as compared with a general SOI-MOSFET.
In case the body region 27 is provided in the thin film SOI-MOSFET, since the excessive holes stored in the channel region 6 can be removed, the withstand voltage between source and drain can be remarkably improved.
In the conventional SOI-MOSFET shown in FIG. 16, however, the body region 27 occupies a considerable amount of a planar area of the silicon layer 3. More specifically, a conventional body region 27 makes it difficult to improve integration of an SOI-MOSFET circuit.
FIG. 19 and FIG. 22 are plan views for explaining a method of manufacturing the SOI-MOSFET of FIG. 16. FIGS. 20 and 21 are sectional views taken along a line K--K and a line L--L in FIG. 19, respectively. FIGS. 23 and 24 are sectional views taken along a line M--M and a line N--N in FIG. 22, respectively.
First, referring to FIG. 19 to FIG. 21, an insulator layer 2 is formed on a silicon substrate 1 and a silicon layer 3 having a low-concentration of p type impurity is formed on the insulator layer 2. The silicon layer 3 in which an SOI-MOSFET is to be formed is isolated as an island through formation of an isolation oxide film 10. Thereafter, a dielectric thin film or a conductor layer is deposited on the silicon layer 3, whereby gate dielectric thin film 4 and a gate electrode 5 are formed by etching using a photoresist pattern 20 as a mask. Furthermore, an area of the semiconductor layer 3 in which a body region 27 is to be formed is masked by a resist layer 29. By selectively implanting ions 30 of arsenic or phosphorus to a higher concentration (for example, 10.sup.18 -10.sup.20 atoms/cm.sup.3), using the resist layers 20 and 29 as masks, n.sup.+ type source region 8 and drain region 9 are formed.
Now referring to FIG. 22 to FIG. 24, after the removal of the resist layers 20 and 29, the semiconductor layer 3 is covered with a resist layer 31, leaving only the area which will be the body region 27. By selectively implanting boron ions 32 to a higher concentration (for example, 10.sup.18 -10.sup.20 atoms/cm.sup.3), using the resist layer 31 as a mask, a p.sup.+ type body region 27 is formed.
Thereafter the resist layer 31 is removed and the semiconductor layer 3 is covered with an interlayer insulating film 11. Contact holes 13a, 13b, 13c and 13d are made in the interlayer insulating film 11. By connecting through the contact holes conductors 15a, 15b, 15c and 15d to the source region 8, the gate electrode 5, the drain region 9 and the body region 27, respectively the conventional SOI-MOSFET shown in FIG. 16 to FIG. 18 is completed.
As described in the foregoing, manufacturing a conventional SOI-MOSFET includes a several steps necessary only for forming the body region 27. More specifically, a conventional body region 27 makes a method of manufacturing SOI-MOSFET complicated.